1. Technical Field
This patent relates, in general, to a flash memory device and, more particularly, to a method of verifying a flash memory device using a page buffer, in which a program or erase verify time can be reduced and an overall driving time can be shortened.
2. Discussion of Related Art
In recent years, there is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and do not require a refresh function of rewriting data at regular intervals. Furthermore, to develop memory devices with a large capacity capable of storing large amounts of data, a high-integrated technique of memory cells has been developed.
To increase the integration of the memory cells, a NAND flash memory device may have a plurality of cells are connected in series to form one string and two strings share one contact. In the NAND flash memory device, program and erase are performed by controlling a threshold voltage of the memory cell while injecting and discharging electrons into and from a floating gate by means of F-N tunneling.
Accordingly, an erased cell has a negative threshold voltage since the electrons of the floating gate are discharged from the cell. A programmed cell has a positive threshold voltage since the electrons are injected into the floating gate. In the case of the NAND flash memory device, however, a fail may occur due to a charge gain or charge loss. Some verifications may be performed in relation to these characteristics. In order to verify whether program and erase have been performed normally, a page buffer is used.
The page buffer serves to receive a large capacity of data from an I/O pad and supply the received data to memory cells or store data of memory cells and then output the stored data. In the past, the page buffer was constructed of a single register in order to temporarily store data. The page buffer is now comprised of a dual register in order to increase the program speed when programming a large capacity of data in the NAND flash memory device.
To perform erase verification of the NAND flash memory device having the page buffer of the dual register structure, a column scan method of confirming whether all cells have been turned on by applying a voltage of 0V to the entire word lines is used. In the column scan method, fail is determined if one cell is turned off.
For the purpose of erase verification, erase verification is performed on a selected bit line through three steps, including precharge, evaluation, and sensing, in the same manner as a common read operation. In the column scan method, erase verification is implemented by dividing the bit lines into even bit lines and odd bit lines. Accordingly, after the even bit lines are verified, the odd bit lines are verified. Therefore, whether erase has been performed is determined through the twice verify process. It results in a long erase verify time.
Meanwhile, in a multi-level cell, threshold voltage distributions of an erase cell have an effect on the threshold voltage of a program cell. Accordingly, a post program is performed on a cell on which erase has been completed. The post program is performed by employing an ISPP method and erase verification is performed after the post program. Accordingly, if the erase verify time becomes long, an overall erase time is lengthened.
Furthermore, at the time of program, a program verify time is lengthened in the same manner as the above. Accordingly, an overall program time becomes long.